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| (R) ISL8120 Data Sheet April 7, 2009 FN6641.1 Dual/n-Phase Buck PWM Controller with Integrated Drivers The ISL8120 integrates two voltage-mode synchronous buck PWM controllers to control a dual independent voltage regulator or a 2-phase single output regulator. It has PLL circuits and can output a phase-shift-programmable clock signal for the system to be expanded to 3-, 4-, 6-, 12- phases with desired interleaving phase shift. It also integrates current sharing control for the power module to operate in parallel, which offers high system flexibility. It has voltage feed forward compensation to maintain a constant loop gain for optimal transient response, especially for applications with a wide input voltage range. Its integrated high speed MOSFET drivers and multi-feature functions provide complete control and protection for a 2/n-phase synchronous buck converter, dual independent regulators, or DDR tracking applications (VDDQ and VTT outputs). The output voltage of a ISL8120-based converter can be precisely regulated to as low as the internal reference voltage 0.6V, with a system accuracy of 0.6% over commercial temperature and line load variations. Channel 2 can track an external ramp signal for DDR/tracking applications. The ISL8120 integrates an internal linear regulator, which generates VCC from input rail for applications with only one single supply rail. The internal oscillator is adjustable from 150kHz to 1.5MHz, and is able to track an external clock signal for frequency synchronization and phase paralleling applications. The integrated Pre-Biased Digital Soft-Start, Differential Remote Sensing Amplifier, and Programmable Input Voltage POR features enhance the value of ISL8120. The ISL8120 protects against overcurrent conditions by inhibiting the PWM operation while monitoring the current with rDS(ON) of the lower MOSFET, DCR of the output inductor, or a precision resistor. It also has a PRE-POR Overvoltage Protection option, which provides some protection to the load device if the upper MOSFET(s) is shorted. See "PRE-POR Overvoltage Protection (PRE-POROVP)" on page 25 for details. The ISL8120's Fault Hand Shake feature protects any channel from overloading/stressing due to system faults or phase failure. The undervoltage fault protection features are also designed to prevent a negative transient on the output voltage during falling down. This eliminates the Schottky diode that is used in some systems for protecting the load device from reversed output voltage damage. Features * Wide VIN Range Operation: 3V to 22V - VCC Operation from 3V to 5.60V * Fast Transient Response - 80MHz Bandwidth Error Amplifier - Voltage-Mode PWM Leading-edge Modulation Control - Voltage Feed-forward * Dual Channel 5V High Speed 4A MOSFET Gate Drivers - Internal Bootstrap Diodes * Internal Linear Regulator Provides a 5.4V Bias from VIN * External Soft-Start Ramp Reference Input for DDR/Tracking Applications * Excellent Output Voltage Regulation - 0.6V 0.6%/0.9% Internal Reference Over Commercial/Industrial Temperature - True Differential Remote Voltage Sensing * Oscillator Programmable from 150kHz to 1.5MHz * Frequency Synchronization * Scale for 1-, 2-, 3-, 4-, 6-, up to 12- Phase with Single Output - Excellent Phase Current Balancing - Programmable Phase Shift Between the 2 Phases Controlled by the ISL8120 and Programmable Phase Shift for Clockout Signal - Interleaving Operation Results in Minimum Input RMS Current and Minimum Output Ripple Current * Fault Hand Shake Capability for High System Reliability * Overcurrent Protection - DCR, rDS(ON), or Precision Resistor Current Sensing - Independent and Average Phase Current OCP * Output Overvoltage and Undervoltage Protections * Programmable Phase Shift in Dual Mode Operation * Digital Soft-Start with Pre-Charged Output Start-up Capability * Power-Good Indication * Dual Independent Channel Enable Inputs with Precision Voltage Monitor and Voltage Feed-forward Capability - Programmable Input Voltage POR and its Hysteresis with a Resistor Divider at EN Input * Over-Temperature Protection * Pre-Power-On-Reset Overvoltage Protection Option * 32 Ld 5x5 QFN Package - Near Chip-Scale Footprint - Enhanced Thermal Performance for MHz Applications * Pb-free (RoHS compliant) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8120 Applications * Power Supply for Datacom/Telecom and POL * Paralleling Power Module VMON1 Pinout ISL8120 (32 LD QFN) TOP VIEW VSEN1+ ISEN1B ISEN1A VSEN1BOOT1 25 24 UGATE1 23 PHASE1 22 LGATE1 33 GND 21 PVCC 20 LGATE2 19 PHASE2 18 UGATE2 17 BOOT2 9 COMP2 10 FB2 11 VMON2 12 VSEN213 VSEN2+ 14 ISEN2B 15 ISEN2A 16 VIN March 20, 2009 FN6641.0 * Wide and Narrow Input Voltage Range Buck Regulators * DDR I and II Applications * High Current Density Power Supplies * Multiple Outputs VRM and VRD COMP1 1 ISET 2 ISHARE 3 EN/VFF1 4 FSYNC 5 FB1 32 31 30 29 28 27 26 Related Literature * Technical Brief TB389 "PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages" Ordering Information PART NUMBER (Note) ISL8120CRZ PART MARKING ISL8120 CRZ TEMP. RANGE (C) 0 to +70 0 to +70 PACKAGE (Pb-free) 32 Ld QFN 32 Ld QFN PKG. DWG. # L32.5x5B L32.5x5B L32.5x5B L32.5x5B EN/VFF2 6 CLKOUT/REFIN 7 PGOOD 8 ISL8120CRZ-T* ISL8120 CRZ ISL8120IRZ ISL8120IRZ-T* ISL8120 IRZ ISL8120 IRZ -40 to +85 32 Ld QFN -40 to +85 32 Ld QFN * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 VCC Block Diagram EN/FF1 VCC PVCC VIN INTERNAL LINEAR REGULATOR POWER-ON RESET (POR) OTP 5.4V 3 CHANNEL 1 REFERENCE VREF = 0.6V VCC 700mV VREF SOFT-START AND FAULT LOGIC FB1 COMP1 OV/UV COMP1 E/A1 7-CYCLE DELAY CHANNEL1 OCP 1.2V VSEN1+ VSEN1UNITY GAIN DIFF AMP1 PGOOD COMP1 108A CURRENT CORRECTION PGOOD VMON1 PGOOD April 7, 2009 OVER-TEMPERATURE PROTECTION (OTP) BOOT1 UGATE1 SAW1 AVG_OCP PHASE1 + PVCC CURRENT CORRECTION AVERAGE OCP ISHARE M/D Control ICSH_ERR (BOTTOM PAD) GND ICSH_ERR IAVG_CS ICS1 LGATE1 PWM1 GATE CONTROL ISL8120 CHANNEL 1 CURRENT SAMPLING ISEN1A ISEN1B FIGURE 1. CHANNEL/PHASE 1 (VDDQ) Block Diagram (Continued) EN/FF2 CLKOUT/REFIN FSYNC ISHARE IAVG_CS+15A CURRENT SHARE BLOCK IAVG_CS OTP POR ICS1 MASTER CLOCK OSCILLATOR GENERATOR ICS2 + AVERAGE CURRENT + IAVG BOOT2 700mV VREF2 M/D CONTROL SAW2 PVCC UGATE2 IAVG_CS+15A ISET RELATIVE PHASE CONTROL ICSH_ERR SAW1 4 VREF VCC FB2 COMP2 VREF VSEN2+ VSEN2UNITY GAIN DIFF AMP2 April 7, 2009 k*VDDQ M/D CONTROL CHANNEL 2 SOFT-START AND FAULT LOGIC AVG_OCP E/A2 7-CYCLE DELAY + - PWM2 GATE CONTROL PHASE2 ISL8120 CURRENT OV/UV COMP2 CHANNEL2 OCP CORRECTION + - PVCC LGATE2 ICS2 CHANNEL 2 GND ISEN2A ISEN2B 108A CURRENT SAMPLING PGOOD COMP2 PGOOD VMON2 M/D = 1: multiphase M/D = 0: DUAL OUTPUT OPERATION IAVG_CS = IAVG or ICS1 IAVG = (ICS1 + ICS2) / 2 ICSH_ERR = (VISARE - VISET)/GCS 0.6V = k*VDDQ FIGURE 2. CHANNEL/PHASE 2 (VTT) ISL8120 Typical Application I (Dual Regulators with DCR Sensing and Remote Sense) VIN VIN_F RCC CF2 VCC LIN CHFIN CF1 PVCC BOOT1 CBOOT1 VIN UGATE1 PHASE1 VOUT1 LGATE1 2k ISEN1A ISEN1B COMP1 RISEN1 10 ZCOMP1 10 Q2 COUT1 Q1 LOUT1 CBIN +3.3 TO +22V CF3 ISL8120 FB1 CLKOUT/REFIN VCC VMON1 VSEN1+ ZFB1 RFB1 ROS1 CSEN1 VSENSE1+ VSENSE1- VSEN1- PGOOD BOOT2 VIN_F CBOOT2 RFS FSYNC UGATE2 PHASE2 VOUT2 LGATE2 2k ISEN2A 10 ISEN2B COMP2 EN2/FF2 EN1/FF1 FB2 ZFB2 RSET ISET ISHARE VMON2 VSEN2+ ROS2 RFB2 CSEN2 VSENSE2+ VSENSE2RISEN2 ZCOMP2 10 Q4 COUT2 Q3 LOUT2 VSEN2GND 5 March 20, 2009 FN6641.0 ISL8120 Typical Application II (Double Data Rate I or II) VIN +3.3 TO +22V RCC CF2 VCC LIN VIN_F CHFIN CF1 PVCC BOOT1 CBOOT1 VIN UGATE1 PHASE1 Q1 LOUT1 2.5V 1.8V (DDR I) (DDR II) VDDQ LGATE1 COUT1 2k ISEN1A ISEN1B COMP1 RISEN1 10 ZCOMP1 10 Q2 CBIN CF3 RFS FSYNC ISL8120 FB1 ZFB1 VMON1 VDDQ VSEN1+ ROS1 RFB1 CSEN1 VSENSE1+ VSENSE1- VSEN1R*(VTT/0.6-1) (See notes below) CLKOUT/REFIN R 1nF BOOT2 VDDQ Or VIN_F CBOOT2 UGATE2 (Or tie REFIN pin to VMON1 pin) PHASE2 Q3 LOUT2 1.25V (DDR I) 0.9V (DDR II) VTT LGATE2 2k ISEN2A Q4 COUT2 ( VDDQ/2) 10 ISEN2B COMP2 RISEN2 ZCOMP1 10 PGOOD FB2 ZFB1 VMON2 RSET ISET ISHARE GND VSEN2+ ROS2 VSEN2- RFB2 CSEN2 VSENSE2+ VSENSE2- Note 1: Set the upper resistor to be a little higher than R*(VDDQ/0.6 - 1) will set the final REFIN voltage (stead state voltage after soft-start) derived from the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start. The other way is to add more delay at EN/FF1 pin to have Channel 2 tracking VDDQ (check the DDR section for more details). Note 2: Another way to set REFIN voltage is to connect VMON1 directly to REFIN pin. 6 March 20, 2009 FN6641.0 ISL8120 Typical Application III (2-Phase Operation with rDS(ON) Sensing and Voltage Trimming) +3V TO +22V VIN LIN CHFIN CF1 RCC VCC PVCC BOOT1 CBOOT1 VIN CF3 UGATE1 PHASE1 COUT1 Q1 LOUT1 VOUT1 CF2 CBIN LGATE1 EN/FF1, 2 ISEN1A Q2 10 ISEN1B COMP1/2 FB1 RSET RISEN1 10 VSENSE1+ VSENSE1- ISL8120 ZCOMP1 ISET ISHARE VMON1/2 VSEN1+ ROS1 VSEN1- DNP RFB1 0 CSEN1 PULLED TO VSENSE1TRIM UP TRIM DOWN PGOOD BOOT2 VIN_F PULLED TO VSENSE1+ CBOOT2 RFS FSYNC UGATE2 PHASE2 Q3 LOUT2 LGATE2 CLKOUT/REFIN ISEN2A Q4 ISEN2B VCC GND FB2 VSEN2+ GND VSEN2- RISEN2 7 March 20, 2009 FN6641.0 ISL8120 Typical Application IV (3-Phase Regulator with Precision Resistor Sensing) VIN +3V TO +22V VCC CF1 VIN RCC PVCC BOOT1 CBOOT2 UGATE1 Q1 LOUT2 VOUT Q2 COUT PHASE1 LGATE1 LIN CF2 VIN_F CIN CF3 ISL8120 EN/FF1 PHASE 2 CLKOUT/REFIN PGOOD ISEN1A ISEN1B COMP1 FB1 RISEN2 10 10 BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A ISEN2B GND EN/FF2 GND VMON1 VSEN1+ VSEN1VCC VSENSE1+ VSENSE1- FSYNC FB2 VMON2 VSEN2+ VCC VSEN2ISHARE ISET R R VCC CF1 VIN FSYNC RFS EN/FF1,2 PGOOD EN/FF1, 2 VIN_F CBOOT3 LOUT3 Q3 UGATE2 PHASE2 BOOT2 RCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 CF2 VIN_F CF3 Q1 CBOOT1 LOUT1 Q2 ISL8120 PHASE 1 AND 3 ISEN1A ISEN1B COMP1/2 FB1 RISEN1 ZCOMP1 ZFB1 Q4 LGATE2 VMON1/2 VSEN1+ RFB1 ROS1 CSEN1 ISEN2A VSEN1ISEN2B RISEN3 VCC GND VCC FB2 VSEN2+ VSEN2GND ISHARE R CLKOUT/REFIN ISET R 8 March 20, 2009 FN6641.0 ISL8120 Typical Application V (4 Phase Operation with DCR Sensing) VIN +3V TO +22V VCC CF1 VIN CLKOUT/REFIN RCC PVCC BOOT1 CBOOT2 UGATE1 PHASE1 LGATE1 PGOOD EN/FF1, 2 VCC VCC VCC VIN_F BOOT2 CBOOT4 LOUT4 Q3 UGATE2 PHASE2 GND FB1 VMON1/2 ISET R LIN VIN_F CIN CF2 CF3 Q1 LOUT2 VOUT1 COUT Q2 ISL8120 ISEN1A VSEN1, 2+ FB2 VSEN1,2- PHASE 2 AND 4 ISEN1B COMP1/2 RISEN2 10 RFB1 ROS1 COS VSENSE1+ VSENSE110 Q4 LGATE2 2ND DIVIDER TO AVOID SINGLE POINT FAILURE FSYNC ISHARE R ISEN2A ISEN2B RISEN4 VCC CF1 VIN FSYNC RFS EN/FF1, 2 PGOOD VIN_F BOOT2 CBOOT3 LOUT3 Q3 UGATE2 PHASE2 RCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 CF2 VIN_F CF3 Q1 CBOOT1 LOUT1 Q2 ISL8120 PHASE 1 AND 3 ISEN1A ISEN1B COMP1/2 FB1 VMON1/2 RISEN1 ZCOMP1 ZFB1 Q4 LGATE2 VSEN1+ ISEN2A VSEN1ISHARE R RFB1 ROS1 CSEN1 RISEN3 VCC VCC VCC ISEN2B FB2 VSEN2+ VSEN2GND CLKOUT/REFIN ISET R 9 March 20, 2009 FN6641.0 ISL8120 Typical Application VI (3-Phase Regulator with Resistor Sensing and 1 Phase Regulator) VIN +3V to +22V VCC CF1 VIN EN/FF2 EN/FF1 PGOOD VCC VIN_F BOOT2 CBOOT4 VOUT2 COUT2 Q4 LGATE2 VSEN1ISEN2A ISET 10 10 RISEN4 ZFB2 ISEN2B R ZCOMP2 FB2 VMON2 VSEN2+ VSENSE2+ VSENSE2CF2 VIN_F VSEN2GND FSYNC ISHARE R VCC LOUT4 Q3 UGATE2 PHASE2 FB1 VMON1 VSEN1+ VSENSE1+ VSENSE110 CLKOUT/REFIN RCC PVCC BOOT1 CBOOT2 UGATE1 PHASE1 LGATE1 Q2 COUT1 Q1 LOUT2 PHASE 2 VOUT1 LIN VIN_F CF2 CIN CF3 ISEN1A ISEN1B COMP1 RISEN2 10 ISL8120 PHASE 2 VCC CF1 VIN FSYNC RFS PGOOD EN/FF1, 2 VIN_F CBOOT3 LOUT3 Q3 UGATE2 PHASE2 BOOT2 RCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 CF3 Q1 CBOOT1 LOUT1 Q2 ISL8120 ISEN1A ISEN1B COMP1/2 FB1 RISEN1 ZCOMP1 ZFB1 Q4 LGATE2 VMON1/2 VSEN1+ RFB1 ROS1 CSEN1 ISEN2A VSEN1ISEN2B RISEN3 VCC GND VCC FB2 VSEN2+ VSEN2ISET VSEN2+ GND R ISHARE PHASE 1 AND 3 CLKOUT/REFIN R 10 March 20, 2009 FN6641.0 ISL8120 Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control) +3V to +22V VIN LIN CIN VCC CF4 VIN PGOOD CLKOUT/REFIN EN/FF1, 2 VIN BOOT2 CBOOT4 LOUT4 Q7 UGATE2 PHASE2 COMP1/2 ZCOMP2 RCC2 PVCC BOOT1 CBOOT3 UGATE1 PHASE1 LGATE1 2k ISEN1A ISEN1B RISEN3 10 10 Q6 COUT2 Q5 LOUT3 VOUT2 CF5 CF6 ISL8120 Q8 2k ISEN2A RISEN4 ISEN2B VSEN2+ FB2 GND VCC VSEN2LGATE2 FB1 VMON1/2 VSEN1+ VSEN1RCSR2 ROS2 ZFB2 RFB2 CSEN2 VSENSE2+ VSENSE2VLOAD 2-PHASE MODULE #1 GND FSYNC ISHARE ISET R R VCC CF1 VIN FSYNC RFS EN/FF1, 2 PGOOD VIN BOOT2 CBOOT2 LOUT2 Q3 UGATE2 PHASE2 RCC1 PVCC BOOT1 UGATE1 PHASE1 LGATE1 2k ISEN1A ISEN1B COMP1/2 FB1 CF2 VIN_F CF3 Q1 CBOOT1 LOUT1 VOUT1 COUT1 Q2 RISEN1 10 ZCOMP1 ZFB1 10 ISL8120 Q4 2k ISEN2A RISEN2 ISEN2B LGATE2 VMON1/2 VSEN1+ VSEN1ISHARE RCSR1 ROS1 RFB1 CSEN1 VSENSE1+ VSENSE1- VSEN2+ GND VCC FB2 VSEN2- 2-PHASE MODULE #2 CLKOUT/REFIN GND ISET R R 11 March 20, 2009 FN6641.0 ISL8120 Typical Application VII (6 Phase Operation with DCR Sensing) +3V TO +22V VIN VCC RCC LIN CF1 CF3 EN/FF1, 2 PGOOD GND VIN_F CBOOT6 LOUT6 VCC FB2 VSEN2+ VSEN2BOOT2 Q3 UGATE2 PHASE2 LGATE2 ISEN2A ISEN2B RISEN6 VCC VIN EN/FF1,2 PGOOD VIN_F CBOOT5 LOUT5 Q3 BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A ISEN2B RISEN5 GND VCC FB2 VSEN2+ VSEN2RCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B COMP1/2 FB1 VMON1/2 VSEN1+ VSEN1FSYNC RISEN2 CF2 VIN_F CBOOT2 LOUT2 GND PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B COMP1/2 FB1 VMON1/2 VSEN1+ VSEN1ISET R FSYNC ISHARE R CF1 CF3 RISEN3 VIN_F CIN CF2 Q1 Q2 CBOOT3 LOUT3 VIN CLKOUT/REFIN ISL8120 PHASE 3 AND 6 VCC Q4 Q1 Q2 ISL8120 Q4 VCC CLKOUT/REFIN PHASE 2 AND 5 GND ISHARE ISET R R VIN_F CF1 CF3 FSYNC EN/FF1, 2 PGOOD VIN_F CBOOT4 LOUT4 Q3 BOOT2 UGATE2 PHASE2 VCC VIN RCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B VMON1 FB1 COMP1/2 CF2 Q1 Q2 RISEN1 10 ZFB1 ZCOMP1 ROS1 RFB1 CSEN1 VSENSE1+ VSENSE1R 10 CBOOT1 LOUT1 VOUT1 COUT1 ISL8120 Q4 LGATE2 ISEN2A ISEN2B RISEN4 GND VCC FB2 VSEN2+ VSEN2- VMON2 VSEN1+ VSEN1ISHARE RFB1 ROS1 PHASE 1 AND 4 GND CLKOUT/REFIN ISET R 12 March 20, 2009 FN6641.0 ISL8120 Typical Application VIIII (4 Outputs Operation with DCR Sensing) VIN +3V TO +22V CF1 CF3 VSENSE4+ RFB4 ROS4 VSENSE4ZFB3 2 2 VIN_F CSEN4 EN/FF2 VSEN2+ VSEN2VMON2 FB2 ZCOMP4 COMP2 PGOOD BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A OUTPUT 3 AND 4 GND ISEN2B RCC VIN_F CBOOT1 LOUT2 VCC RCC LIN PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B CF2 Q1 Q2 CBOOT3 LOUT3 VIN_F CIN VIN CLKOUT/REFIN VOUT3 COUT3 ISL8120 (PHASE 3 and 6) COMP1 FB1 VMON1 VSEN1+ VSEN1ISHARE/ISET EN/FF1 R FSYNC RISEN3 ZFB3 RFB3 ROS3 CSEN3 2 2 COUT4 CBOOT6 LOUT6 VOUT4 Q3 VSENSE3+ VSENSE3- Q4 RISEN6 CF1 CF3 EN/FF1, 2 PGOOD VIN_F CBOOT2 LOUT5 Q3 BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A ISEN2B RISEN5 GND VCC FB2 VSEN2+ VSEN2- VCC VIN PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B CF2 Q1 Q2 VOUT2 COUT2 ISL8120 (PHASE 2 and 5) Q4 COMP1/2 ZCOMP2 FB1 ZFB2 VMON1/2 VSEN1+ VSEN1CLKOUT/REFIN FSYNC ISHARE/ISET ROS2 RISEN2 2 RFB2 CSEN2 2 VSENSE2+ VSENSE2- OUTPUT 2 GND R VIN_F CF1 CF3 FSYNC EN/FF1, 2 PGOOD VIN_F CBOOT4 LOUT4 Q3 BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A ISEN2B RISEN4 GND VCC FB2 VSEN2+ VSEN2OUTPUT 1 GND VCC VIN RCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B VMON1 FB1 COMP1/2 VMON2 VSEN1+ ROS1 RFB1 ROS1 RFB1 CSEN1 VSENSE1+ VSENSE1R CF2 Q1 Q2 RISEN1 2 ZFB1 ZCOMP1 2 CBOOT1 LOUT1 VOUT1 COUT1 ISL8120 (PHASE 1 and 4) Q4 VSEN1ISHARE/ISET CLKOUT/REFIN 13 March 20, 2009 FN6641.0 ISL8120 Absolute Maximum Ratings Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . . . . . . -0.3V to +36V Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V BOOT to PHASE Voltage, VBOOT - VPHASE . . -0.3V to VCC +0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Thermal Information Thermal Resistance (Typical Notes 1, 2) JA(C/W) JC(C/W) 32 Ld QFN Package . . . . . . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 22V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V Boot to Phase Voltage (Overcharged), VBOOT - VPHASE . . . . . .<6V Commercial Ambient Temperature Range. . . . . . . . . . 0C to +70C Industrial Ambient Temperature Range . . . . . . . . . . .-40C to +85C Maximum Junction Temperature Range . . . . . . . . . . . . . . . . +125C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Nominal Supply VIN Current Nominal Supply VIN Current Shutdown Supply PVCC Current Shutdown Supply VCC Current Recommended Operating Conditions, Unless Otherwise Noted. SYMBOL TEST CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNITS IQ_VIN IQ_VIN IPVCC IVCC VIN = 20V; VCC = PVCC; No Load; FSW = 500kHz VIN = 3.3V;VCC = PVCC; No Load; FSW = 500kHz EN = 0V, PVCC = 5V EN = 0V, VCC = 3V 11 8 0.5 7 15 12 1 10 20 14 1.4 12 mA mA mA mA INTERNAL LINEAR REGULATOR Maximum Current (Note 3) IPVCC PVCC = 4V TO 5.6V PVCC = 3V TO 4V Saturated Equivalent Impedance (Note 3) PVCC Voltage Level POWER-ON RESET Rising VCC Threshold Falling VCC Threshold Rising PVCC Threshold ISL8120CRZ ISL8120IRZ Falling PVCC Threshold System Soft-start Delay (Note 3) ENABLE Turn-On Threshold Voltage Hysteresis Sink Current IEN_HYS 0.75 25 0.8 30 0.86 35 V A tSS_DLY After PLL, VCC, and PVCC PORs, and EN(s) above their thresholds 2.85 2.65 2.85 2.85 2.65 384 2.97 2.75 2.97 3.05 2.75 V Cycles V V V RLDO PVCC P-Channel MOSFET (VIN = 5V) IPVCC = 0mA to 250mA 5.1 250 150 1 5.4 5.6 mA mA V 14 March 20, 2009 FN6641.0 ISL8120 Electrical Specifications PARAMETER Undervoltage Lockout Hysteresis (Note 3) Recommended Operating Conditions, Unless Otherwise Noted. (Continued) SYMBOL VEN_HYS IEN_SINK REN_SINK IEN_SINK = 5mA TEST CONDITIONS VEN_RTH = 10.6V; VEN_FTH = 9V RUP = 53.6k, RDOWN = 5.23k Sink Current Sink Impedance OSCILLATOR Oscillator Frequency Range Oscillator Frequency Total Variation Peak-to-Peak Ramp Amplitude Linear Gain of Ramp Over VEN Ramp Peak Voltage Peak-to-Peak Ramp Amplitude Peak-to-Peak Ramp Amplitude Ramp Amplitude Upon Disable Ramp Amplitude Upon Disable Ramp DC Offset VRAMP GRAMP VRAMP_PEAK VRAMP VRAMP VRAMP VRAMP VRAMP_OS RFS = 100k, Figure 21 VCC = 5V; -40C < TA <+85C VCC = 5V, VEN = 0.8V GRAMP = VRAMP/VEN VEN = VCC VEN = VCC = 5.4V, RUP = 2k VEN = VCC = 3V; RUP = 2k VEN = 0V; VCC = 3.5V to 5.5V VEN = 0V; VCC < 3.4V 150 344 -9 1 1.25 VCC - 1.4 3 0.6 1 VCC - 2.4 1 V VP-P VP-P VP-P VP-P V 377 1500 406 +9 kHz kHz % VP-P MIN (Note 4) TYP 1.5 15 65 MAX (Note 4) UNITS V mA FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP Synchronization Frequency PLL Locking Time Input Signal Duty Cycle Range (Note 3) PWM Minimum PWM OFF Time Current Sampling Blanking Time (Note 3) REFERENCE Channel 1 Reference Voltage (Include Error and Differential Amplifiers' Offsets) VREF1 ISL8120CRZ -0.6 ISL8120IRZ -0.7 Channel 2 Reference Voltage (Include Error and Differential Amplifiers' Offsets) VREF2 ISL8120CRZ -0.75 ISL8120IRZ -0.75 ERROR AMPLIFIER DC Gain (Note 3) Unity Gain-Bandwidth (Note 3) Input Common Mode Range (Note 3) Output Voltage Swing Slew Rate (Note 3) Input Current (Note 3) SR_EA IFB VCC = 5V RL = 10k, CL = 100pF, at COMP Pin Positive Direction Into the FB pin UGBW_EA RL = 10k, CL = 100pF, at COMP Pin RL = 10k, CL = 100pF, at COMP Pin -0.2 0.85 20 100 98 80 VCC - 1.8 VCC - 1.0 dB MHz V V V/s nA 0.6 0.95 0.6 0.75 0.6 0.7 0.6 0.6 V % V % V % V % tMIN_OFF tBLANKING 310 345 175 410 ns ns VCC = 5.4V (2.97V) VCC = 5.4V (2.97V); FSW = 400kHz; 10 150 105 90 1500 kHz s % 15 March 20, 2009 FN6641.0 ISL8120 Electrical Specifications PARAMETER Output Sink Current Output Source Current Disable Threshold (Note 3) DIFFERENTIAL AMPLIFIER DC Gain (Note 3) Unity Gain Bandwidth (Note 3) Negative Input Source Current (Note 3) Maximum Source Current for Current Sharing (Typical Application VIII) (Note 3) UG_DA UGBW_DA IVSENIVSEN1RVSEN+_to _VSEN0 -0.2 VVSENVMON1, 2 = Tri-State VCC - 0.4 VSEN1- Source Current for Current Sharing when parallel multiple modules each of which has its own voltage loop Unity Gain Amplifier 0 5 100 350 dB MHz nA A Recommended Operating Conditions, Unless Otherwise Noted. (Continued) SYMBOL ICOMP ICOMP VVSENTEST CONDITIONS MIN (Note 4) TYP 3 6 VCC - 0.4 MAX (Note 4) UNITS mA mA V Input Impedance Output Voltage Swing (Note 3) Input Common Mode Range (Note 3) Disable Threshold (Note 3) GATE DRIVERS Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance OVERCURRENT PROTECTION Channel Overcurrent Limit (Note 3) Channel Overcurrent Limit 1 VCC - 1.8 VCC - 1.8 M V V V RUGATE RUGATE RLGATE RLGATE 45mA Source Current 45mA Sink Current 45mA Source Current 45mA Sink Current 1.0 1.0 1.0 0.4 ISOURCE ISOURCE VCC = 2.97V to 5.6V VCC = 5V; ISL8120CRZ VCC = 5V; ISL8120IRZ 94 89 1.16 108 108 108 1.20 50 122 122 1.22 A A A V mV Share Pin OC Threshold Share Pin OC Hysteresis (Note 3) CURRENT SHARE Internal Balance Accuracy (Note 3) Internal Balance Accuracy (Note 3) External Current Share Accuracy (Note 3) POWER GOOD MONITOR Undervoltage Falling Trip Point Undervoltage Rising Hysteresis Overvoltage Rising Trip Point Overvoltage Falling Hysteresis PGOOD Low Output Voltage Sinking Impedance VOC_SET VCC = 2.97V to 5.6V (comparator offset included) VOC_SET_HYS VCC = 2.97V to 5.6V (comparator offset included) VCC = 2.97V and 3.6V, 1% Resistor Sense, 10mV Signal VCC = 4.5V and 5.6V, 1% Resistor Sense, 10mV Signal VCC = 2.97V and 5.6V, 1% Resistor Sense, 10mV Signal 5 5 5 % % % VUVF VUVR_HYS VOVR VOVF_HYS Percentage Below Reference Point Percentage Above UV Trip Point Percentage Above Reference Point Percentage below OV Trip Point IPGOOD = 2mA IPGOOD = 2mA -15 -13 4 -11 % % 11 13 4 15 % % 0.35 70 V 16 March 20, 2009 FN6641.0 ISL8120 Electrical Specifications PARAMETER Maximum Sinking Current (Note 3) OVERVOLTAGE PROTECTION OV Latching Up Trip Point OV Non-Latching Up Trip Point (Note 3) LGATE Release Trip Point OVER-TEMPERATURE PROTECTION Over-Temperature Trip (Note 3) Over-Temperature Release Threshold (Note 3) NOTES: 3. Limits should be considered typical and are not production tested 4. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 150 125 C C EN/FF= UGATE = LATCH Low, LGATE = High EN/FF = Low, UGATE = Low, LGATE = High EN/FF = Low/HIGH, UGATE = Low, LGATE = Low 118 120 113 87 122 % % % Recommended Operating Conditions, Unless Otherwise Noted. (Continued) SYMBOL TEST CONDITIONS VPGOOD <0.8V MIN (Note 4) TYP 10 MAX (Note 4) UNITS mA 17 March 20, 2009 FN6641.0 ISL8120 Functional Pin Descriptions GND (Pin 33) The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad provides a return path for the low-side MOSFET drives and internal power circuitries as well as all analog signals. Connect this pad to the circuit ground with the shortest possible path (more than 5 to 6 vias to the internal ground plane, placed on the soldering pad are recommended). will lock to an external frequency source if this pin is connected to a switching square pulse waveform, typically the CLKOUT input signal from another ISL8120 or an external clock. The internal oscillator synchronizes with the leading edge of the input signal. EN/FF1, EN/FF2 (Pins 4, 6) These pins have triple functions. The voltage on EN/FF_ pin is compared with a precision 0.8V threshold for system enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel can be disabled independently. By connecting these pins to the input rail through a voltage resistor divider, the input voltage can be monitored for UVLO (undervoltage lockout ) function. The undervoltage lockout and its hysteresis levels can be programmed by these resistor dividers. The voltages on these pins are also fed into the controller to adjust the sawtooth amplitude of each channel independently to realize the feed-forward function. Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins (EN/FF_) are pulled low to communicate the information to other cascaded ICs. VIN (Pin 16) This pin is the input of the internal linear regulator. It should be tied directly to the input rail. When used with an external 5V supply, this pin should be tied directly to PVCC. The internal linear device is protected against reverse bias generated by the remaining charge of the decoupling capacitor at PVCC when losing the input rail. VCC (Pin 26) This pin provides bias power for the analog circuitry. An RC filter is recommended between the connection of this pin to a 3V to 5.6V bias (typically PVCC). R is suggested to be a 5 resistor. And in 3.3V applications, the R could be shorted to allow the low end input in concerns of the VCC falling threshold. The VCC decoupling capacitor C is strongly recommended to be as large as a 10F ceramic capacitor. This pin can be powered either by the internal linear regulator or by an external voltage source. PGOOD (Pin 8) Provides an open drain Power-Good signal when both channels are within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON1/2) of the internal differential amplifiers. BOOT1, 2 (Pins 25, 17) This pin provides the bootstrap bias for the high-side driver. Internal bootstrap diodes connected to the PVCC pin provide the necessary bootstrap charge. Its typical operational voltage range is 2.5V to 5.6V. ISEN1A, ISEN2A (Pins 27, 15) These pins are the non-inverting (+) inputs of the current sensing amplifiers to provide rDS(ON), DCR, or precision resistor current sensing together with the ISEN1B, ISEN2B pins. UGATE1, UGATE2 (Pin 24, 18) These pins provide the drive for the high-side devices and should be connected to the MOSFETs' gates. ISEN1B, ISEN2B (Pins 28, 14) These pins are the inverting (-) inputs of the current sensing amplifiers to provide rDS(ON), DCR, or precision resistor current sensing together with the ISEN1A, ISEN2A pins. Refer to "Typical Application III (2-Phase Operation with rDS(ON) Sensing and Voltage Trimming)" on page 7 for rDS(ON) sensing set up and "Typical Application V (4 Phase Operation with DCR Sensing)" on page 9 for DCR sensing set up. PHASE1, PHASE2 (Pins 23,19) Connect these pins to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. These pins represent the return path for the high-side gate drives. PVCC (Pin 21) This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side drives. Its operational voltage range is 3V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10F. ISET (Pin 2) This pin sources a 15A offset current plus the average current of both channels in multiphase mode or only Channel 1's current in independent mode. The voltage (VISET) set by an external resistor (RISET) represents the average current level of the local active channel(s). LGATE1, LGATE2 (Pins 22, 20) These pins provide the drive for the low-side devices and should be connected to the MOSFETs' gates. FSYNC (Pin 5) The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal oscillator 18 ISHARE (Pin 3) This pin is used for current sharing purposes and is configured to current share bus representing all modules' March 20, 2009 FN6641.0 ISL8120 average current. It sources 15A offset current plus the average current of both channels in multiphase mode or Channel 1's current in independent mode. The share bus (ISHARE pins connected together) voltage (VISHARE) set by an external resistor (RISHARE) represents the average current level of all active channel(s). The ISHARE bus voltage compares with each reference voltage set by each RISET and generates current share error signal for current correction block of each cascaded controller. The share bus impedance RISHARE should be set as RISET/NCTRL (RISET divided by number of active current sharing controllers). There is a 1.2V threshold for average overcurrent protection on this pin. VISHARE is compared with a 1.2V threshold for average overcurrent protections. For full-scale current, RISHARE should be 1.2V/123A = ~10k. Typically 10k is used for RSHARE and RSET. operations, all other SLAVE phases' COMP pins can tie to the MASTER phase's COMP1 pin (1st phase), which modulates each phase's PWM pulse with a single voltage feedback loop. While the error amplifier is not disabled, an independent compensation network is required for each cascaded IC. VSEN1+, VSEN2+ (Pins 29, 13) These pins are the positive inputs of the standard unity gain operational amplifier for differential remote sense for the corresponding channel (Channels 1 and 2), and should be connected to the positive rail of the load/processor. These pins can also provide precision output voltage trimming capability by pulling a resistor from this pin to the positive rail of the load (trimming down) or the return (typical VSEN1-, VSEN2- pins) of the load (trimming up). The typical input impedance of VSEN+ with respect to VSEN- is 500k. By setting the resistor divider connected from the output voltage to the input of the differential amplifier, the desired output voltage can be programmed. To minimize the system accuracy error introduced by the input impedance of the differential amplifier, a resistor below 1k is recommended to be used for the lower leg (ROS) of the feedback resistor divider. With VSEN2- pulled within 700mV of VCC, the corresponding error amplifier is disabled and VSEN2+ is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal. See "DDR and Dual Mode Operation" on page 32 for details. CLKOUT/REFIN (Pin 7) This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal to synchronize with other ISL8120(s) with its VSEN2- pulled within 700mV of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase) operation. When the VSEN2- pin is not within 700mV of VCC, ISL8120 is in dual mode (dual independent PWM output). The clockout signal of this pin is not available in this mode, but the ISL8120 can be synchronized to external clock. In dual mode, this pin works as the following two functions: 1. An external reference (0.6V target only) can be in place of the Channel 2's internal reference through this pin for DDR/tracking applications (see "Internal Reference and System Accuracy" on page 33). 2. The ISL8120 operates as a dual-PWM controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on REFIN (see "DDR and Dual Mode Operation" on page 32). VSEN1-, VSEN2- (Pins 30, 12) These pins are the negative inputs of standard unity gain operational amplifier for differential remote sense for the corresponding regulator (Channels 1and 2), and should be connected to the negative rail of the load/processor. When VSEN1-, VSEN2- are pulled within 700mV of VCC, the corresponding error amplifier and differential amplifier are disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels determine the relative phases between the internal controllers as well as the CLKOUT signal. See "DDR and Dual Mode Operation" on page 32 for details. When configured as multiple power modules (each module with independent voltage loop) operating in parallel, in order to implement the current sharing control, a resistor (100 typ) needs to be inserted between the VSEN1- pin and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor), as shown in the "Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)" on page 11. This introduces a correction voltage for the modules with lower load current to keep the current distribution balanced among modules. The module with the highest load current will automatically become the master module. The recommended value for the March 20, 2009 FN6641.0 FB1, FB2 (Pins 32, 10) These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1, 2 with the compensation feedback network. No direct connection between FB and VMON pins is allowed. With VSEN2- pulled within 700mV of VCC, the corresponding error amplifier is disabled and the amplifier's output is high impedance. FB2 is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal. See "DDR and Dual Mode Operation" on page 32. COMP1, COMP2 (Pins 1, 9) These pins are the error amplifier outputs. They should be connected to FB1, FB2 pins through desired compensation networks when both channels are operating independently. When VSEN1-, VSEN2- are pulled within 700mV of VCC, the corresponding error amplifier is disabled and its output (COMP pin) is high impedance. Thus, in multiphase 19 ISL8120 VSEN1- resistor is 100 and it should not be large in order to keep the unit gain amplifier input impedance compatibility. MODE 5: With VSEN2- pulled within 700mV of VCC and FB2 pulled to ground, the internal channels are 180 out-of-phase and operate in 2-phase single output mode (5A). The CLKOUT/REFIN pin (rising edge) also signals out clock with 60 phase shift relative to the Channel 1's clock signal (falling edge of PWM) for 6-phase operation with two other ISL8120s (5B). When the share pins are not connected to each other for the three ICs in sync, two of which can operate in Mode 5A (3 independent outputs can be generated (Mode 5D)) and Modes 3 and 4 (to generate 4 independent outputs (Mode 5C)) respectively. MODE 6: With VSEN2- pulled within 700mV of VCC, FB2 pulled high and VSEN2+ pulled low, the internal channels (as 1st and 3rd Phase, respectively) are 240 out-of-phase and operate in 3-phase single output mode, combined with another ISL8120 at MODE 2B. The CLKOUT/REFIN pin signals out 120 relative phases to the falling edge of Channel 1's clock signal to synchronize with the second ISL8120's Channel 1 (as 2nd Phase). MODE 7: With VSEN2- pulled within 700mV of VCC and FB2 and VSEN2+ pulled high, the internal channel is 180 out-of-phase. The CLKOUT/REFIN pin (rising edge) signals out 90 relative phase to the Channel 1's clock signal (falling edge of PWM) to synchronize with another ISL8120, which can operate at Mode 3, 4, 5A, or 7A. A 4-phase single output converter can be constructed with two ISL8120s operating in Mode 5A or 7A (Mode 7A). If the share bus is not connected between ICs, each IC could generate an independent output (Mode 7B). When the second ISL8120 operates as two independent regulators (Mode 3) or in DDR mode (Mode 4), then a three independent output system is generated (Mode 7C). Both ICs can also be constructed as a 3-phase converter (0, 90, and 180, not a equal phase shift for 3-phase) with a single phase regulator (270). MODE 8: The output CLKOUT signal allows expansion for 12-phase operation with the cascaded sequencing, as shown in Table 1. No external clock is required in this mode for the desired phase shift. MODE 9: With an external clock, the part can be expanded for 5, 7, 8, 9 10 and 11 phase single output operation with the desired phase shift. VMON1, VMON2 (Pins 31, 11) These pins are outputs of the unity gain amplifiers. They are connected internally to the OV/UV/PGOOD comparators. These pins should be connected to the FB1, FB2 pins by a standard feedback network when both channels are operating independently. When VSEN1-, VSEN2- are pulled within 700mV of VCC, the corresponding differential amplifier is disabled and its output (VMON pin) is high impedance. In such an event, the VMON pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for both of the UV/OV comparator and output voltage feedback. Modes of Operation There are 9 typical operation modes depending upon the signal levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-, FB2, and CLKOUT/REFIN. MODE 1: The IC is completely disabled when EN1/FF1 and EN2/FF2 are pulled below 0.8V. MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high (Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pulled low (Mode 2B), the ISL8120 operates as a single phase regulator. The current sourcing out from the ISHARE pin represents the first channel current plus 15A offset current. MODE 3: When VSEN2- is used as a negative sense line, both channels' phase shift depends upon the voltage level of CLKOUT/REFIN. When the CLKOUT/REFIN pin is within 29% to 45% of VCC, Channel 2 delays 0 over Channel 1 (Mode 3A); when within 45% to 62% of VCC, 90delay (Mode 3B); when greater than 62% to VCC, 180 delay (Mode 3C). Refer to the "DDR and Dual Mode Operation" on page 32. MODE 4: When VSEN2- is used as a negative remote sense line, and CLKOUT/REFIN is connected to an external voltage ramp lower than the internal soft-start ramp and lower than 0.6V, the external ramp signal will replace Channel 2's internal soft-start ramp to be tracked at start-up, controller operating in DDR mode. The controller will use the lowest voltage among the internal 0.6V reference, the external voltage in CLKOUT/REFIN pin and the soft-start ramp signal. Channel 1 is delayed 60 behind Channel 2. Refer to the "DDR and Dual Mode Operation" on page 32. 20 March 20, 2009 FN6641.0 ISL8120 TABLE 1. 1ST IC (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, Bi-DIRECTION) ISHARE (I/O) REPRESENTS WHICH CHANNEL(S) CURRENT N/A MODES OF OPERATION EN1/ EN2/ FF1 FF2 VSEN2(I) (I) FB2 (I) (I) MODE 1 2A 0 0 0 1 - VSEN2 + (I) - CLKOUT/REFIN WRT 1ST (I or O) - 2ND CHANNEL WRT 1ST (O)* VMON1 = VMON2 to Keep PGOOD Valid VMON1 = VMON2 to Keep PGOOD Valid 0 90 180 -60 180 180 180 180 240 180 180 OPERATION OPERATION OUTPUT (See MODE MODE Description of 3RD IC of 2ND IC for Details) DISABLED SINGLE PHASE SINGLE PHASE DUAL REGULATOR DUAL REGULATOR DUAL REGULATOR DDR MODE 2-PHASE 6-PHASE 3 OUTPUTs 4 OUTPUTs 3-PHASE 4-PHASE 2 OUTPUTs (1st IC in Mode 7A) 3 OUTPUTs (1st IC in Mode 7A) 12-PHASE 5, 7, 8, 9, 10, 11, or (PHASE >12) ACTIVE ACTIVE ACTIVE 2B 1 0 - - - - 1ST CHANNEL - - 3A 3B 3C 4 5A 5B 5C 5D 6 7A 7B - - 5A 5A 5A 2B 5A or 7A 5A or 7A 5A or 7A 5A or 7A 3 or 4 - 7C - - VCC VCC VCC 90 BOTH CHANNELS 180 3, 4 - 8 9 Cascaded IC Operation MODEs 5A+5A+7A+5A+5A+5A/7A, No External Clock Required External Clock or External Logic Circuits Required for Equal Phase Interval NOTE: "2ND CHANNEL WRT 1ST" is referred to as "channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells". For example, 90 with 2ND CHANNEL WRT 1ST means channel 2 lags channel 1 by 90 degree; -60 with 2ND CHANNEL WRT 1ST means channel 2 leads channel 1 by 60 degree. 21 March 20, 2009 FN6641.0 ISL8120 CH1 UG (1ST IC) D 180 1-D CH2 UG (1ST IC) 90 CLKOUT (1ST IC) 90 CH1 UG (2ND IC) CH2 UG (2ND IC) D D 50% 180 D 4 PHASE TIMING DIAGRAM (MODE 7A) CH1 UG (1ST IC) D 240 1-D CH2 UG (1ST IC) 120 CLKOUT (1ST IC) 120 CH1 UG (2ND IC) D D 50% 1-D CH2 UG(2ND IC, OFF, EN2/FF2 = 0) 3-PHASE TIMING DIAGRAM (MODE 6) VCC VSEN2- VSEN2+ VMON2 FB2 COMP2 CLKOUT/REFIN 700mV DIFF AMP2 UV/OV COMP2 VREF2 = VREF ERROR AMP2 CLOCK GENERATOR AND RELATIVE PHASES CONTROL CHANNEL 1 PWM CONTROL BLOCK CHANNEL 2 PWM CONTROL BLOCK FIGURE 3. SIMPLIFIED RELATIVE PHASES CONTROL 22 March 20, 2009 FN6641.0 ISL8120 Functional Description Initialization Initially, the ISL8120 Power-On Reset (POR) circuits continually monitor the bias voltages (PVCC and VCC) and the voltage at the EN pin. The POR function initiates soft-start operation 384 clock cycles after the EN pin voltage is pulled to be above 0.8V, all input supplies exceed their POR thresholds and the PLL locking time expires, as shown in Figure 4. The enable pin can be used as a voltage monitor and to set desired hysteresis with an internal 30A sinking current going through an external resistor divider. The sinking current is disengaged after the system is enabled. This feature is especially designed for applications that require higher input rail POR for better undervoltage protection. For example, in 12V applications, RUP = 53.6k and RDOWN = 5.23k will set the turn-on threshold (VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with 1.6V hysteresis (VEN_HYS). During shutdown or fault conditions, the soft-start is reset quickly while UGATE and LGATE change states immediately (<100ns) upon the input drop below falling POR. HIGH = ABOVE POR; LOW = BELOW POR VCC POR PVCC POR EN1/FF1 POR PLL LOCKING AND 384 Cycles SOFT-START OF CHANNEL 1 Voltage Feed-forward Other than used as a voltage monitor described in the previous section, the voltages applied to the EN/FF pins are also fed to adjust the amplitude of each channel's individual sawtooth. The amplitude of each channel's sawtooth is set to 1.25 times the corresponding EN/FF voltage upon its enable (above 0.8V). This helps to maintain a constant gain ( G M = VIN D MAX V RAMP ) contributed by the modulator and the input voltage to achieve optimum loop response over a wide input voltage range. The sawtooth ramp offset voltage is 1V (equal to 0.8V*1.25), and the peak of the sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the ramp has a maximum peak-to-peak amplitude of VCC - 2.4V (equal to 3V); so the feed-forward voltage effective range is typically 3x as the ramp amplitude ranges from 1V to 3V. A 384 cycle delay is added after the system reaches its rising POR and prior to the soft-start. The RC timing at the EN/FF pin should be sufficiently small to ensure that the input bus reaches its static state and the internal ramp circuitry stabilizes before soft-start. A large RC could cause the internal ramp amplitude not to synchronize with the input bus voltage during output start-up or when recovering from faults. It is recommended to use open drain or open collector to gate this pin for any system delay, as shown in Figure 5. The multiphase system can immediately turn off all ICs under fault conditions of one or more phases by pulling all EN/FF pins low. Thus, no bouncing occurs among channels at fault and no single phase could carry all current and be over stressed. VCC POR PVCC POR EN2/FF2 POR AND 384 Cycles SOFT-START OF CHANNEL 2 FIGURE 4. SOFT-START INITIALIZATION LOGIC V EN_HYS R UP = ---------------------------I EN_HYS R *V UP EN_REF R DOWN = -------------------------------------------------------------V EN_FTH - V EN_REF VCC V EN_FTH = V EN_RTH - V EN_HYS V RAMP = LIMIT(V CC_FF x G RAMP , VCC - 1.4V - V RAMP_OFFSET ) GRAMP = 1.25 VCC - 1.4V 0.8V VCC_FF LIMITER UPPER LIMIT SAWTOOTH AMPLITUDE (VRAMP) LOWER LIMIT (RAMP OFFSET) VIN VRAMP_OFFSET = 1.0V 0.8V RUP EN/FF 384 Clock Cycles SOFT-START SYSTEM DELAY RDOWN IEN_HYS = 30A OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1) FIGURE 5. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT 23 March 20, 2009 FN6641.0 ISL8120 VIN ISL8120 2-PHASE EN/FF1 EN/FF2 RUP ISL8120 2-PHASE EN/FF1 EN/FF2 RDOWN 0.0V -100mV FIRST PWM PULSE SS Settling at VREF + 100mV VOUT 1280 t SS = -----------F SW 384 t SS_DLY ----------F SW R V EN_HYS = --------------------------------------------------------UP I N EN_HYS PHASE FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE FIGURE 7. SOFT-START WITH VOUT = 0V While EN/FF is pulled to ground, a constant voltage (0.8V) is fed into the ramp generator to maintain a minimum peak-to-peak ramp. UV FIRST PWM PULSE SS Settling at VREF + 100mV VOUT Since the EN/FF pins are pulled down under fault conditions, the pull-up resistor (RUP) should be scaled to sink no more than 5mA current from EN/FF pin. Essentially, the EN/FF pins cannot be directly connected to VCC. -100mV FIGURE 8. SOFT-START WITH VOUT = UV Soft-start The ISL8120 has two independent digital soft-start circuitry with fixed 1280 switching cycles. The soft-start time is inversely proportional to the switching frequency and is determined by the 1280-cycle digital counter. Refer to Figure 7. The full soft-start time from 0V to 0.6V can be estimated using Equation 1. 1280 t SS = -----------f SW (EQ. 1) OV = 113% FIRST PWM PULSE VOUT TARGET VOLTAGE FIGURE 9. SOFT-START WITH VOUT BELOW OV BUT ABOVE FINAL TARGET VOLTAGE The ISL8120 has the ability to work under a pre-charged output (see Figure 8). The output voltage would not be yanked down during pre-charged start-up. If the pre-charged output voltage is greater than the final target level but prior to 113% setpoint, the switching will not start until the output voltage reduces to the target voltage and the first PWM pulse is generated (see Figure 9). The maximum allowable pre-charged level is 113%. If the pre-charged level is above 113% but below 120%, the output will hiccup between 113% (LGATE turns on) and 87% (LGATE turns off) while EN/FF is pulled low. If the pre-charged load voltage is above 120% of the targeted output voltage, then the controller will be latched off and not be able to power-up. For above-target level pre-charged start-up, the output voltage would not change until the end of the soft-start. If the initial dip is below the UV level, the LGATE could be turned off. In such an event, the body-diode drop of the low-side FET will be sensed and could potentiality cause an OCP event for rDS(ON) current sensing applications. Power-Good CHANNEL 1 UV/OV CHANNEL 2 UV/OV END OF SS1 END OF SS2 SS1_PERIOD SS2_PERIOD OR PGOOD AND AND +20% +13% VMON1, 2 +9% VREF -9% -13% PGOOD PGOOD latch off after 120% OV FIGURE 10. POWER-GOOD THRESHOLD WINDOW 24 March 20, 2009 FN6641.0 ISL8120 VMON1 113% 87% OR EN/FF1 VMON1>120% OR VMON2 113% 87% EN/FF2 VMON2 > 120% multiphase MODE = HIGH AND AND FORCE LGATE1 HIGH conditions of EN/FF = LOW and the output voltage above 113% (all VMON pins and EN pins are tied together) and turns off after the output drops below 87%. Thus, in a high phase count application (Multiphase Mode), all cascaded ICs can latch off simultaneously via the EN pins (EN pins are tied together in multiphase mode), and each IC shares the same sink current to reduce the stress and eliminate the bouncing among phases. The UV functionality is not enabled until the end of soft-start. In a UV event, if the output drops below -13% of the target level due to some reason (cases when EN/FF is not pulled low) other than OV, OC, OT, and PLL faults, the lower MOSFETs will turn off to avoid any negative voltage ringing. 120% VOUT 3 CYCLES 3 CYCLES OR AND FORCE LGATE2 HIGH FIGURE 11. FORCE LGATE HIGH LOGIC Both channels share the same PGOOD output. Either of the channels indicating out-of-regulation will pull-down the PGOOD pin. The Power-Good comparators monitor the voltage on the VMON pins. The trip points are shown in Figure 10. PGOOD will not be asserted until after the completion of the soft-start cycle of both channels. If Channels 1 or 2 are not used, the Power-Good can stay in operation by connecting 2 channels' VMON pins together. The PGOOD pulls low upon both EN/FF's disabling it if one of the VMON pins' voltage is out of the threshold window. PGOOD will not pull low until the fault presents for three consecutive clock cycles. In Dual/DDR application, if the turn-off channel pre-charges its VMON within the PGOOD threshold window, it could indicate Power-Good, however, the PGOOD signal can pull low with an external PNP or PMOS transistor via the EN/FF of the corresponding off channel. PGOOD UV OV LATCH UGATE AND EN/FF LATCH LOW FIGURE 12. PGOOD TIMING UNDER UV AND OV PRE-POR Overvoltage Protection (PRE-POR-OVP) When both the VCC and PVCC are below PORs (not including EN POR), the UGATE is low and LGATE is floating (high impedance). EN/FF has no control on LGATE when below PORs. When above PORs, the LGATE would not be floating but toggling with its PWM pulses. An internal 10k resistor, connected in between PHASE and LGATE nodes, implements the PRE-POR-OVP circuit. The output of the converter that is equal to phase node voltage via output inductors is then effectively clamped to the low-side MOSFET's gate threshold voltage, which provides some protection to the microprocessor if the upper MOSFET(s) is shorted during start-up, shutdown, or normal operations. For complete protection, the low-side MOSFET should have a gate threshold that is much smaller than the maximum voltage rating of the load. The PRE-POR-OVP works against pre-biased start-up when pre-charged output voltage is higher than the threshold of the low-side MOSFET, however, it can be disabled by placing a 2k resistor from LGATE to ground. Overvoltage and Undervoltage Protection The Overvoltage (OV) and Undervoltage (UV) protection circuitry monitor the voltage on the VMON pins. OV protection is active from the beginning of soft-start. An OV condition (>120%) would latch IC off (the high-side MOSFET to latch off permanently; the low-side MOSFET turns on immediately at the time of OV trip and then turns off permanently after the output voltage drops below 87%). The EN/FF and PGOOD are also latched low at OV event. The latch condition can be reset only by recycling VCC. In Dual/DDR mode, each channel is responsible for its own OV event with the corresponding VMON as the monitor. In multiphase mode, both channels respond simultaneously when either triggers an OV event. There is another non-latch OV protection (113% of target level). At the condition of EN/FF low and the output over 113% OV, the lower side MOSFET will turn on until the output drops below 87%. This is to protect the overall power trains in case of only one channel of a multiphase system detecting OV. The low-side MOSFET always turns on at the Over-Temperature Protection (OTP) When the junction temperature of the IC is greater than +150C (typically), both EN/FF pins pull low to inform other cascaded channels via their EN/FF pins. All connected EN/FFs stay low and release after the IC's junction temperature drops below +125C (typically), with a +25C hysteresis (typical). 25 March 20, 2009 FN6641.0 ISL8120 Current Loop When the ISL8120 operates in 2-phase mode, the current control loop keeps the channel's current in balance. After 175ns blanking period with respect to the falling edge of the PWM pulse of each channel, the voltage developed across the DCR of the inductor, rDS(ON) of the low-side MOSFETs, or a precision resistor, is filtered and sampled for 175ns. The current (ICS1/ICS2) is scaled by the RISEN resistor and provides feedback proportional to the average output current of each channel. For DCR sensing, the sampling current ICS can be derived from Equation 2: V OUT 1-D IL + --------------- * --------------- - t MIN_OFF * DCR 2F L SW ICS = ---------------------------------------------------------------------------------------------------------------RISEN DCR SENSING IOUT1 VOUT L1 C DCR1 R RISEN1 RISEN1 RISEN2 ISEN1B ISEN1A DCR1 AMP 700mV ICS1 ISEN1A ISEN2A DCR2 AMP ICS2 ISEN2B PHASE1 VOUT L1 DCR1 IOUT1 where IL is the inductor DC current, DCR is its DC resistance, and tMIN_OFF is 350ns. For low-side MOSFET rDS(ON) sensing, the ICS can be derived from Equation 3: V OUT 1-D IL + --------------- * --------------- - t MIN_OFF * r DS ( ON ) 2F L SW ICS = ------------------------------------------------------------------------------------------------------------------------RISEN (EQ. 3) In multiphase mode (VSEN2- pulled high), the scaled output currents from both active channels are combined to create an average current reference (IAVG) which represents average current of both channel outputs as calculated in Equation 4. ICS1 + ICS2 IAVG = ----------------------------------2 (EQ. 4) (EQ. 2) rDS(ON) SENSING PHASE1 PHASE2 DCR2 R IOUT2 VOUT L2 C ISEN1B VCC VSEN2- VSEN2+ E/A IAVG_CS +15A ISHARE CHANNEL 1 PWM CONTROL BLOCK CHANNEL 1 CURRENT CORRECTION BLOCK + + 2 + + ICSH_ERR IAVG_CS IAVG CURRENT SHARE BLOCK - CHANNEL 2 CURRENT CORRECTION BLOCK CHANNEL 2 PWM CONTROL BLOCK ISET CHANNEL 1 IAVG_CS +15A RISET 1.2V AVG_OC COMP SOFT-START & FAULT LOGIC ITRIP=108A OC2 COMP 7 CYCLES DELAY CHANNEL 2 SOFT-START & FAULT LOGIC VISHARE 7 CYCLES DELAY ITRIP=108A OC1 COMP IAVG = (ICS1 + ICS2) / 2 IAVG_CS = IAVG or ICS1 ICSH_ERR = (VISARE - VISET)/GCS FIGURE 13. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION 26 March 20, 2009 FN6641.0 ISL8120 The signal IAVG is then subtracted from the individual channel's scaled current (ICS1 or ICS2) to produce a current correction signal for each channel. The current correction signal keeps each channel's output current contribution balanced relative to the other active channel. For multiphase operation, the share bus (VISHARE) represents the average current of all active channels and compares with each IC's average current (IAVG_CS equals to IAVG or ICS1 depending upon the configuration, represented by VISET) to generate current share error signal (ICS_ERR) for each individual channel. Each current correction signal is then subtracted from the error amplifier output and fed to the individual channel PWM circuits. When both channels operate independently, the average function is disabled and generates zero average current (IAVG = 0), and the current correction block of Channel 2 is also disabled. The IAVG_CS is the Channel 1 current ICS1. The Channel 1 makes any necessary current correction by comparing its channel current (represented by VISET) with the share bus (VISHARE). When the share bus does not connect to other ICs, the ISET and ISHARE pins can be shorted together and grounded via a single resistor to ensure zero share error. Note that the common mode input voltage range of the current sense amplifiers is VCC - 1.8V. Therefore, the rDS(ON) sensing should be used for applications with output voltage greater than VCC - 1.8V. For example, an application of 3.3V output is suggested to use rDS(ON) sensing. In addition, the R-C network components (for DCR sensing) are selected such that the RC time constant matches the inductor L/DCR time constant. Otherwise, it could cause undershoot/overshoot during load transient and start-up. C is typically set to 0.1F or higher, while R is calculated with Equation 5. L R = ----------------------C * DCR (EQ. 5) Figure 13 shows a simple and flexible configuration for both rDS(ON) and DCR sensing. Current Share Control in Multiphase Single Output The IAVG_CS is the average current of both channels (IAVG, 2-phase mode) or only Channel 1 (ICS1, any other modes). ISHARE and ISET pins source a copy of IAVG_CS with 15A offset, for example, the full-scale will be 123A. If one single external resistor is used as RISHARE connecting the ISHARE bus to ground for all the ICs in parallel, RISHARE should be set equal to RISET/NCTRL (where NCNTL is the number of the ISL8120 controllers in parallel or multiphase operations), and the share bus voltage (VISHARE) set by the RISHARE represents the average current of all active channels. Another way to set RISHARE is to put one resistor in each IC' s ISHARE pin and use the same value with RISET ( RISHARE = RISET), in which case the total equivalent resistance value is also RISET/NCTRL. The voltage (VISET) set by RISET represents the average current of the corresponding device and compared with the share bus (VISHARE). The current share error signal (ICSH_ERR) is then fed into the current correction block to adjust each channel's PWM pulse accordingly. The current share function provides at least 10% overall accuracy between ICs, 5% within the IC when using a 1% resistor to sense a 10mV signal. The current share bus works for up to 12-phase. ERROR AMP 1 ICS1 IAVG_CS ERROR AMP 2 - + + - VERROR1 ICS2 IAVG_CS ICSH_ERR - + CURRENT MIRROR BLOCK SHARE BUS RISHARE ISET RISET ISHARE ICSH_ERR - + VERROR2 VCC 700mV CURRENT MIRROR BLOCK IAVG = (ICS1 + ICS2) / 2 IAVG_CS = IAVG or ICS1 IDROOP + 15A = IAVG_CS + 15A = ISET = ISHARE RISHARE=RISET/NCTRL VSEN2- FIGURE 14. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION 27 March 20, 2009 FN6641.0 ISL8120 For multiphase implementation, one single error amplifier should be used for the voltage loop. Therefore, all other channels' error amplifiers should be disabled with their corresponding VSEN- pulled to VCC, as shown in Figure 16. is combined with RCSR to determine the current sharing regulation range. The generated correction voltage on RCSR is suggested to be within 5% of VREF (0.6V) to avoid fault triggering of UV/OV and PGOOD during dynamic events. There are basically two options for the configuration of the communication wires between the modules. Each of option has its own unique features. One option is to synchronize all the modules where the system has 3 analog signal communication wires (CLKOUTSYNC, ISHARE, EN/FF). In this option, all the modules are synchronized and the phase shift can also be configured to optimal to reduce the input current ripple by interleaving effects. The connections of these three wires allows the system to be started at the same time and achieve good current balance in start-up without overcurrent trip. To have different phase shift, each module has different circuitry configuration to program the phase shift, thus to make only one standard module is difficult. Current Share Control Loop in Multi-Module with Independent Voltage Loop The power module controlled by ISL8120 with its own voltage loop can be paralleled to supply one common output load with its integrated Master-Slave current sharing control, as shown in "Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)" on page 11. A resistor RCSR needs to be inserted between VSEN1- pin and the lower resistor of the voltage sense resistor divider for each module. With this resistor, the correction current sourcing from VSEN1- pin will create a voltage offset to maintain even current sharing among modules. The recommended value for the VSEN1- resistor RCSR is 100 and it should not be large in order to keep the unity gain amplifier input pin impedance compatibility. The maximum source current from VSEN1- pin is 350A, which ISHARE VCC R3 10k Q1 R2 3.3k R4 10k Q2 Q3 ISHARE BUS GND ISL8120 COMP R1 1k GND VOUT MODULE 1 GND ISHARE VCC R3 10k Q1 R2 3.3k GND MODULE 2 R4 10k Q2 Q3 ISHARE BUS GND ISL8120 COMP R1 1k Q1: MMBT3904 Q2: MMBT3904 Q3: 2N7002 FIGURE 15. SINGLE COMMUNICATION WIRE CONNECTION 28 March 20, 2009 FN6641.0 ISL8120 VCC VSEN1/2- COM1/2 ISET ISL81201 ISHARE RISET2 VSEN2ISET COM1/2 VSEN1+ VSEN1/2- COM1/2 ISET ISL81203 ISHARE RISET3 ISL81202 VSEN1ISHARE RISET1 RISHARE1 SHARE BUS RISHARE2 RISHARE3 RISHARE_ = RISET_ FIGURE 16. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION The second option for multi-module parallel system is to have only one signal (ISHARE) wire connection. The signal wire connection scheme is targeted for a N+1 system, where each module is a standard one that can be paralleled to build up power systems with different capacity, and each module can start-up at different time, and each module can be shut down and removed without the system shutdown. Figure 15 shows some extra circuits needed for such a parallel module system (each module with independant voltage feedback loop where only one analog signal (ISHARE) wire is connected between the module) besides the circuits shown in "Typical Application VIIII (4 Outputs Operation with DCR Sensing)" on page 13. The circuitry shown in Figure 15 is to ensure the successful start-up of the system with the individual module starting up at different time. With this circuitry, each module's local ISHARE signal is connected to the system share bus only when it starts switching (finishing of pre-biased start-up). In addition, when the module is shut off, its ISHARE signal will be removed from the ISHARE bus. The validated signal transistors shown in Figure 15 are: MMBT3904 for Q1 and Q2; 2N7002 for Q3. With the circuits of Figure 15 implemented, the system can also be further implemented with the CLKOUT-SYNC connection to have the modules synchornized and phaseshifted, which is the third option of system configuration. However, the lose of CLKOUT signal will cause the shutdown of the other module receiving the signal. Compared with the second option (single wire (ISHARE) connection), this option has one more wire connection, but all the modules are synchronized and phase-shifted. In summary, the communication wire connection in parallel systems offers flexibility. Each configuration option has its own unique features. The selection of the connections of the conmmunication wire should be based upon evaluation of the priorities of system requirements and features, such as reliability, number of wire connections, synchronizations and fault tolerance, etc. 29 In dual mode, the current sharing block for current sharing of modules with independant voltage loop is disabled. Overcurrent Protection The OCP function is enabled at start-up. When both channels operate independently, the average function is disabled and generates zero average current (IAVG = 0). The Channel 2 current (ICS2) is compared with ITRIP (108A) as its own independent overcurrent protection and the 7 clock cycles delay is bypassed. The Channel 1's current (ICS1) plus 15A offset forms a voltage (VISHARE) with an external resistor RISHARE and compares with a precision 1.2V threshold for OCP; while the 108A OCP comparator with 7-cycle delay is also activated. In multiphase operation, the VISHARE represents the average current of all active channels and compares with the ISHARE pin precision 1.2V threshold to determine the overcurrent condition. At the same time, each channel has additional overcurrent trip point at 108A with 7-cycle delay for phase overcurrent protection. This scheme helps protect against loss of channel(s) in multi-phase mode so that no single channel could carry more than 108A in such event. See Figure 13. Note that it is not necessary for the RISHARE to be scaled to trip at the same level as the 108A OCP comparator if the application allows. Typically the ISHARE pin average current protection level should be higher than the phase current protection level. For instance, when Channel 1 operates independently, the OC trip set by 1.2V comparator can be lower than 108A trip point as shown in Equation 6. I OC V OUT 1 - D --------- + --------------- * --------------- - t MIN_OFF * DCR L 2F SW N R ISEN1 = --------------------------------------------------------------------------------------------------------------------I TRIP 1.2V R ISHARE = -------------I TRIP R ISET = R ISHARE N CNTL (EQ. 6) where N is the number of phases; NCNTL is the number of the ISL8120 controllers in parallel or multiphase operations; March 20, 2009 FN6641.0 ISL8120 ITRIP = 108A; IOC is the load overcurrent trip point; tMIN_OFF is the minimum Ugate turn off time that is 350ns; RISHARE in Equation 6 represents the total equivalent resistance in ISHARE pin bus of all ICs in multiphase or module parallel operation. For the RISEN chosen for OCP setting, the final value is usually higher than the number calculated from Equation 6. The reason of which is practical especially for low DCR applications since the PCB and inductor pad soldering resistance would have large effects in total impedance, affecting the DCR voltage to be sensed. When OCP is triggered, the controller pulls EN/FF low immediately to turn off UGATE and LGATE. For overload and hard short condition, the overcurrent protection reduces the regulator RMS output current much less than full load by putting the controller into hiccup mode. A delay time, equal to 3 soft-start intervals, is inserted to allow the disturbance to be cleared out. After the delay time, the controller then initiates a soft-start interval. If the output voltage comes up and returns to the regulation, PGOOD transitions high. If the OC trip is exceeded during the soft-start interval, the controller pulls EN/VFF low again. The PGOOD signal will remain low and the soft-start interval will be allowed to expire. Another soft-start interval will be initiated after the delay interval. If an overcurrent trip occurs again, this same cycle repeats until the fault is removed. 5V 2.65V TO 5.6V 2 1F VCC PVCC VIN 10F 3V TO 26.4V Z1 Z2 FIGURE 17. INTERNAL REGULATOR IMPLEMENTATION The LDO is capable of supplying 250mA with regulated 5.4V output. In 3.3V input applications, when the VIN pin voltage is 3V, the LDO can still supply 150mA while maintaining LDO output voltage higher than VCC falling threshold to keep IC operating. Figure 18 shows the LDO voltage drop under different load current. However, its thermal capability should not be exceeded. The power dissipation inside the IC could be estimated with Equation 7. 6.0 5.5 5.0 PVCC (V) 4.5 4.0 3.5 3.0 2.5 2.0 2.5 3.0 3.5 Iq IS AROUND 15mA 4.0 4.5 5.0 5.5 VIN PIN VOLTAGE (V) 6.0 6.5 7.0 PVCC @ 140mA + Iq PVCC @ 250mA + Iq PVCC @ 100mA + Iq Internal Series Linear and Power Dissipation The VIN pin is connected to PVCC with an internal series linear regulator. The PVCC and VIN pins should have the recommended bypass ceramic capacitors (10F) connected to GND for proper operation. The internal linear regulator's input (VIN) can range between 3V to 22V. PVCC pin is the output of the internal linear regulator and it provides power for both the internal MOSFET drivers through the PVCC pin. VCC pin is the bias input for the IC small signal analog circuitry. By connecting PVCC to VCC pin, the internal linear regulator supplies bias power to VCC. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from the analog circuitry. When VIN drops below 5.0V, the pass element will saturate; PVCC will track VIN with a dropout of the linear regulator. When used with an external 5V supply, the VIN pin is recommended to be tied directly to PVCC. FIGURE 18. PVCC vs VIN VOLTAGE P IC = ( VIN - PVCC ) I VIN + P DR (EQ. 7) Q G1 * N Q1 Q G2 * N Q2 I VIN = ----------------------------- + ----------------------------- * PVCC * F SW + I Q_VIN V GS2 V GS1 30 March 20, 2009 FN6641.0 ISL8120 P DR = P DR_UP + P DR_LOW R HI1 R LO1 P Qg_Q1 P DR_UP = -------------------------------------- + --------------------------------------- * --------------------R HI1 + R EXT1 R LO1 + R EXT1 2 R HI2 R LO2 P Qg_Q2 P DR_LOW = -------------------------------------- + --------------------------------------- * --------------------R HI2 + R EXT2 R LO2 + R EXT2 2 Q G1 * PVCC 2 P Qg_Q1 = -------------------------------------- * F SW * N Q1 V GS1 Q G2 P Qg_Q2 = -------------------------------------- * F SW * N Q2 V GS2 R GI1 R EXT2 = R G1 + ------------N Q1 R GI2 R EXT2 = R G2 + ------------N Q2 * PVCC 2 (EQ. 8) Oscillator The Oscillator is a sawtooth waveform, providing for leading edge modulation with 350ns minimum dead time. The oscillator (Sawtooth) waveform has a DC offset of 1.0V. Each channel's peak-to-peak of the ramp amplitude is set proportional the voltage applied to its corresponding EN/FF pin. See "Voltage Feed-forward" on page 23. 1,600 SWITCHING FREQUENCY (kHz) 1,400 1,200 1,000 800 600 400 200 0 20 40 60 80 100 120 140 160 180 200 220 240 260 R_FS (k ) where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ_VIN is the driver's total quiescent current with no load at drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. To keep the IC within its operating temperature range, an external power resistor could be used in series with VIN pin to bring the heat out of the IC, or and external LDO could be used when necessary. PVCC BOOT D CGD RHI1 RLO1 G RG1 RGI1 CGS S PHASE Q1 CDS FIGURE 21. RFS vs SWITCHING FREQUENCY Frequency Synchronization and Phase Lock Loop The FSYNC pin has two primary capabilities: fixed frequency operation and synchronized frequency operation. By tying a resistor (RFSYNC) to GND from the FSYNC pin, the switching frequency can be set at any frequency between 150kHz and 1.5MHz. The frequency setting curve shown in Figure 21 is provided to assist in selecting the correct value for RFSYNC. By connecting the FSYNC pin to an external square pulse waveform (such as the CLOCK signal, typically 50% duty cycle from another ISL8120), the ISL8120 will synchronize its switching frequency to the fundamental frequency of the input waveform. The maximum voltage to the FSYNC pin is VCC + 0.3V. The Frequency Synchronization feature will synchronize the leading edge of CLKOUT signal with the falling edge of Channel 1's PWM clock signal. The CLKOUT is not available until the PLL locks. The locking time is typically 130s for FSW = 500kHz. EN/VFF1 is released for a soft-start cycle until the FSYNC stabilized and the PLL is in locking. The PLL circuits control only EN/FF1, and control Channel 2's soft-start instead of EN/FF2. Therefore, it is recommended to connect all EN/FF pins together in multiphase configuration. The loss of a synchronization signal for 13 clock cycles causes the IC to be disabled until the PLL returns locking, at which point a soft-start cycle is initiated and normal operation resumes. Holding FSYNC low will disable the IC. UGATE FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC D CGD RHI2 RLO2 LGATE G RG2 RGI2 CGS GND S Q2 CDS FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH 31 March 20, 2009 FN6641.0 ISL8120 Differential Amplifier for Remote Sense VSEN+ 20k RDIF = 500k 20k VSEN- 20k 20k FIGURE 22. EQUIVALENT DIFFERENTIAL AMPLIFER The differential remote sense buffer has a precision unity gain resistor matching network, which has a ultra low offset of 1mV. This true remote sensing scheme helps compensate the droop due to load on the positive and negative rails and maintain the high system accuracy of 0.6%. The output of the remote sense buffer is connected directly to the internal OV/UV comparator. As a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in Figure 24. The VMON pin should be connected to the FB pin by a standard feedback network. Since the input impedance of VSEN+ pin in respect to VSEN- pin is about 500k, it is highly recommended to include this impedance into calculation and use 100 or less for the lower leg (ROS) of the feedback resistor divider to optimize system accuracy. Note that any RC filter at the inputs of the differential amplifier will contribute as a pole to the overall loop compensation. VOUT As some applications will not need the differential remote sense, the output of the remote sense buffer can be disabled and be placed in high impedance by pulling VSEN- within 700mV of VCC. In such an event, the VMON pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for the UV/OV comparator and the output regulation. The resistor divider ratio should be the same as the one for the output regulation so that the correct voltage information is provided to the OV/UV comparator. Figure 23 shows the differential sense amplifier can be directly used as a monitor without pulling VSEN- high. DDR and Dual Mode Operation If the CLKOUT/REFIN is less than 800mV, an external soft-start ramp (0.6V) can be in parallel with the Channel 2's internal soft-start ramp for DDR/tracking applications (DDR Mode). The output voltage (typical VTT output) of Channel 2 tracks with the input voltage (typical VDDQ*(1+k) from Channel 1) at the CLKOUT/REFIN pin. As for the external input signal and internal reference signal (ramp and 0.6V), the one with the lowest voltage will be the one to be used as the reference comparing with FB signal. So in DDR configuration, VTT channel should start-up later after its internal soft-start ramp in which way the VTT will track the voltage on REFIN pin derived from VDDQ. This can be achieved by adding more filtering at EN//FF1 compared with EN/FF2. RFB ROS ROS RFB ZCOMP VCC VSEN+ GND VSENPGOOD VMON FB COMP 700mV GAIN=1 VREF OV/UV COMP ERROR AMP PGOOD FIGURE 23. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION 32 March 20, 2009 FN6641.0 ISL8120 VSENSE- (REMOTE) VOUT (LOCAL) 10 VSENSE+ (REMOTE) GND (LOCAL) CSEN 10 ROS RFB ZFB VCC VSENVSEN+ VMON ZCOMP PGOOD FB COMP 700mV GAIN=1 VREF OV/UV COMP ERROR AMP PGOOD FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION Since the UV/OV comparator uses the same internal reference 0.6V, to guarantee UV/OV and Pre-charged start-up functions of Channel 2, the target voltage derived from Channel 1 (VDDQ) should be scaled close to 0.6V, and it is suggested to be slightly above (+2%) 0.6V with an external resistor divider, which will have Channel 2 use the internal 0.6V reference after soft-start. Any capacitive load at REFIN pin should not slow down the ramping of this input 150mV lower than the Channel 2' internal ramp. Otherwise, the UV protection could be fault triggered prior to the end of the soft-start. The start-up of Channel 2 can be delayed to avoid such situation happening, if high capacitive load presents at REFIN pin for noise decoupling. During shutdown, Channel 2 will follow Channel 1 until both channels drops below 87%, at which point both channels enter UV protection zone. Depending on the loading, Channel 1 might drop faster than Channel 2. To solve this race condition, Channel 2 can either power up from Channel 1 or bridge the Channel 1 with a high current Schottky diode. If the system requires to shutdown both channels when either has a fault, tying EN/FF1 and EN/FF2 will do the job. In DDR mode, Channel 1 delays 60 over Channel 2. In Dual mode, depending upon the resistor divider level of REFIN from VCC, the ISL8120 operates as a dual-PWM controller for two independent regulators with a phase shift, as shown in Table 2. The phase shift is latched as VCC raises above POR and cannot be changed on the fly. TABLE 2. MODE DDR Dual Dual Dual DECODING REFIN RANGE <29% of VCC 29% to 45% of VCC 45% to 62% of VCC 62% to VCC PHASE for CHANNEL REQUIRED 2 WRT CHANNEL 1 REFIN -60 0 90 180 0.6V 37% VCC 53% VCC VCC VCC VDDQ PHASE-SHIFTED CLOCK VSEN2- k*R CLKOUT/REFIN ISL8120 STATE MACHINE R 700mV VTT k = ------------ - 1 0.6V Internal SS 0.6V FB2 E/A2 FIGURE 25. SIMPLIFIED DDR IMPLEMENTAION Internal Reference and System Accuracy The internal reference is set to 0.6V. Including bandgap variation and offset of differential and error amplifiers, it has an accuracy of 0.6% over commercial temperature range, and 0.9% over industrial temperature range. While the remote sense is not used, its offset (VOS_DA) should be included in the tolerance calculation. Equations 9 and 10 show the worst case of system accuracy calculation. VOS_DA should set to zero when the differential amplifier is in the loop, the differential amplifier's input impedance (RDIF) is typically 500k with a tolerance of 20% (RDIF%) and can be neglected when ROS is less than 100. To set a precision setpoint, ROS can be scaled by two paralleled resistors. Figure 26 shows the tolerance of various output voltage regulation for 1%, 0.5%, and 0.1% feedback resistor 33 March 20, 2009 FN6641.0 ISL8120 dividers. Note that the farther the output voltage setpoint away from the internal reference voltage, the larger the tolerance; the lower the resistor tolerance (R%), the tighter the regulation. R FB ( 1 - R% ) %min = ( Vref ( 1 - Ref% ) - V OS_DA ) 1 + --------------------------------------- R OSMAX (EQ. 9) 1 R OSMAX = ---------------------------------------------------------------------------------------------------1 1 ---------------------------------------- + --------------------------------------------------R OS ( 1 + R% ) R DIF ( 1 + R DIF % ) R FB ( 1 - R% ) %max = ( Vref ( 1 - Ref% ) - V OS_DA ) 1 + --------------------------------------- R OSMIN (EQ. 10) 1 R OSMIN = ----------------------------------------------------------------------------------------------1 1 -------------------------------------- + ------------------------------------------------R OS ( 1 - R % ) R DIF ( 1 - R DIF % ) OUTPUT REGULATION (%) 2.5 2.0 1.5 0.5% 1.0 0.5 0.0 -0.5 -1.0 0.5% -1.5 -2.0 -2.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) 1% 0.1% 0.1% R% = 1% FIGURE 26. OUTPUT REGULATION WITH DIFFERENT RESISTOR TOLERANCE FOR Ref% = 0.6% All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 34 April 7, 2009 ISL8120 Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07 4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA 25 24 32 1 5.00 3 .30 0 . 15 17 (4X) 0.15 16 9 8 0.10 M C A B 4 32X 0.23 - 0.05 + 0.07 32X 0.40 0.10 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( 3. 30 ) ( 28X 0 . 5 ) SIDE VIEW (32X 0 . 23 ) C ( 32X 0 . 60) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 35 March 20, 2009 FN6641.0 |
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